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Патенты сотрудников кафедры и лаборатории

Отечественные патенты

  1. Бабин Д.Н., Мазуренко И.Л., Уранцев А.В., Холоденко А.Б. Способ идентификации факта речевой активности оператора. Заявка на патент 99103468/ 28(003418) решение от 29.12.99.
  2. Бабин Д.Н., Дудецкий В.Н., Мазуренко И.Л., Уранцев А.В. и др. Патент на изобретение "Устройство для синтеза и анализа речевых сигналов". №94045004/09 (045160) от 20.12.96, дата заявки 23.12.94, патентодержатель НПЦ "Ракурс".

 

Патенты США

  1. Andreev A.E., Gribok S.V., Bolotov A.A. Memory BISR architecture for a slice. United States Patent: 7,430,694, September 30, 2008.
  2. Andreev A.E., Nikitin A.A., Neznanov I.V., Scepanovic R. Method and apparatus for mapping design memories to integrated circuit layout. United States Patent: 7,424,687, September 9, 2008.
  3. Andreev A.E., Nikitin A.A., Scepanovic R. Method and system for outputting a sequence of commands and data described by a flowchart. United States Patent: 7,415,691, August 19, 2008.
  4. Andreev A.E., Bolotov A.A., Scepanovic R. Memory timing model with back-annotating. United States Patent: 7,415,686, August 19, 2008.
  5. Uzhakov S.V., Aleshin S.V., Medvedeva M.M. Method and system for improving aerial image simulation speeds. United States Patent: 7,406,675, July 29, 2008.
  6. Andreev A.E., Panteleev P.A., Nikitin A.A. Method and system for mapping netlist of integrated circuit to design. United States Patent: 7,404,166, July 22, 2008.
  7. Aleshin S.V., Medvedeva M.M., Rodin S.B., Egorov E.E. Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes. United States Patent: 7,401,318, July 15, 2008.
  8. Galatenko A.V., Gasanov E.E., Lyalin I.V. Method and apparatus for controlling congestion during integrated circuit design resynthesis. United States Patent: 7,401,313, July 15, 2008.
  9. Galatenko A.V., Gasanov E.E., Zolotykh A.A. Method and apparatus for performing logical transformations for global routing. United States Patent: 7,398,486, July 8, 2008.
  10. Panteleev P.A., Nikitin A.A., Andreev A.E. Method and system for converting netlist of integrated circuit between libraries. United States Patent: 7,380,223, May 27, 2008.
  11. Nikitin A.A., Neznanov I.V., Andreev A.E. RRAM controller built in self test memory. United States Patent: 7,356,743, April 8, 2008.
  12. Golubtsov I., Aleshin S.V., Scepanovic R., Rodin S.B., Medvedeva M.M., Uzhakov S.V., Egorov E.E., Strelkova N. Method and system for analyzing the quality of an OPC mask. United States Patent: 7,340,706, March 4, 2008.
  13. Nikitin A.A., Andreev A.E. Method for evaluating logic functions by logic circuits having optimized number of and/or switches. United States Patent: 7,328,423, February 5, 2008.
  14. Andreev A.E., Gribok S.V., Bolotov A.A. Memory BISR controller architecture. United States Patent: 7,328,382, February 5, 2008.
  15. Nikitin A.A., Andreev A.E., Scepanovic R. Verification of RRAM tiling netlist. United States Patent: 7,315,993, January 1, 2008.
  16. Andreev A.E., Vikhliantsev I.A., Vukovic V. Data stream frequency reduction and/or phase shift. United States Patent: 7,313,660, December 25, 2007.
  17. Andreev A.E., Gribok S., Bolotov A.A. Master controller architecture. United States Patent: 7,308,633, December 11, 2007.
  18. Andreev A.E., Scepanovic R. System and method for efficiently testing a large random access memory space. United States Patent: 7,305,597, December 4, 2007.
  19. Andreev A.E., Bolotov A.A., Scepanovic R. Memory mapping for parallel turbo decoding. United States Patent: 7,305,593, December 4, 2007.
  20. Andreev A.E., Gribok S., Bolotov A.A. RRAM communication system. United States Patent: 7,283,385, October 16, 2007.
  21. Nikitin A.A., Andreev A.E., Vikhliantsev I.A. Digital gaussian noise simulator. United States Patent: 7,263,470, August 28, 2007.
  22. Rodin S.B., Aleshin S.М., Medvedeva M.G. OPC edge correction based on a smoothed mask design. United States Patent: 7,260,814, August 21, 2007.
  23. Nikitin A.A., Andreev A.E. Method for optimizing execution time of parallel processor programs. United States Patent: 7,257,807, August 14, 2007.
  24. Galatenko A.V., Gasanov E.E., Zolotykh A.A., Lyalin I.V. Multiple buffer insertion in global routing. United States Patent: 7,257,791, August 14, 2007.
  25. Andreev A.E., Pavisic I., Bolotov A.A. Density driven layout for RRAM configuration module. United States Patent: 7,246,337, July 17, 2007.
  26. Zolotykh A.A., Gasanov E.E., Galatenko A.V., Lyalin I.V. Ramptime propagation on designs with cycles. United States Patent: 7,246,336, July 17, 2007.
  27. Andreev A.E., Bolotov A.A., Scepanovic R. Search engine for large-width data. United States Patent: 7,231,383, June 12, 2007.
  28. Nikitin A.A., Andreev A.E., Bolotov A.A. Process and apparatus for memory mapping. United States Patent: 7,219,321, May 15, 2007.
  29. Andreev A.E., Bolotov A.A., Scepanovic R. Method and BIST architecture for fast memory testing in platform-based integrated circuit. United States Patent: 7,216,278, May 8, 2007.
  30. Andreev A.E., Nikitin A.A., Vikhliantsev I.A. Process and apparatus for placing cells in an IC floorplan. United States Patent: 7,210,113, April 24, 2007.
  31. Andreev A.E., Vikhliantsev I.A., Pavisic I. Memory tiling architecture. United States Patent: 7,207,026, April 17, 2007.
  32. Andreev A.E., Nikitin A.A., Scepanovic R. RRAM memory timing learning tool. United States Patent: 7,200,826, April 3, 2007.
  33. Andreev A.E., Bolotov A.A. Sequential tester for longest prefix search engines. United States Patent: 7,200,785, April 3, 2007.
  34. Andreev A.E., Pavisic I., Bolotov A.A. Compact custom layout for RRAM column controller. United States Patent: 7,194,717, March 20, 2007.
  35. Andreev A.E., Gashkov S.B., Sedelev O.B., Nikitin A.A. RRAM flipflop rcell memory generator. United States Patent: 7,193,905, March 20, 2007.
  36. Andreev A.E., Bolotov A.A., Scepanovic R. FIFO memory with single port memory modules for allowing simultaneous read and write operations. United States Patent: 7,181,563, February 20, 2007.
  37. Andreev A.E., Nikitin A.A., Scepanovic R. Yield driven memory placement system. United States Patent: 7,168,052, January 23, 2007.
  38. Gashkov S.B., Andreev A.E. Method for constructing logic circuits of small depth and complexity for operation of inversion in finite fields of characteristic 2. United States Patent: 7,167,886, January 23, 2007.
  39. Andreev A.E., Neznanov I.V., Nikitin A.A., Scepanovic R., Vikhliantsev I. Memory generation and placement. United States Patent: 7,155,688, December 26, 2006.
  40. Lyalin I.V., Zolotykh A.A., Gasanov E.E., Galatenko A.V. Method of selecting cells in logic restructuring. United States Patent: 7,146,591, December 5, 2006.
  41. Gasanov E.E., Lyalin I.V., Galatenko A.V., Zolotykh A.A. Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths. United States Patent: 7,111,267, September 19, 2006.
  42. Andreev A.E., Nikitin A.A., Scepanovic R. Process and apparatus for fast assignment of objects to a rectangle. United States Patent: 7,111,264, September 19, 2006.
  43. Nikitin A.A., Andreev A.E. Optimizing depths of circuits for Boolean functions. United States Patent: 7,103,868, September 5, 2006.
  44. Galatenko A.V., Kudryavtsev V.B., Gasanov E.E. Process and apparatus for placement of megacells in ICs design. United States Patent: 7,103,865, September 5, 2006.
  45. Andreev A.E., Scepanovic R., Vukovic V. Decomposer for parallel turbo decoding, process and integrated circuit. United States Patent: 7,096,413, August 22, 2006.
  46. Andreev A.E., Pavisic I., Ivanovic L. Method and system for classifying an integrated circuit for optical proximity correction. United States Patent: 7,093,228, August 15, 2006.
  47. Nikitin A.A., Andreev A.E. Method and apparatus of IC implementation based on C++ language description. United States Patent: 7,082,593, July 25, 2006.
  48. Andreev A.E., Bolotov A.A., Radovanovic N. Built-in functional tester for search engines. United States Patent: 7,082,561, July 25, 2006.
  49. Andreev A.E., Bolotov A.A., Vikhliantsev I.A. Integrated circuit and process for identifying minimum or maximum input value among plural inputs. United States Patent: 7,072,922, July 4, 2006.
  50. Andreev A.E., Vikhliantsev I.A., Scepanovic R. Controller architecture for memory mapping. United States Patent: 7,065,606, June 20, 20 06.
  51. Andreev A.E., Vikhliantsev I.A., Bolotov A.A. Method for generating tech-library for logic function. United States Patent: 7,062,726, June 13, 2006.
  52. Andreev A.E., Vikhliantsev I.A., Scepanovic R. Pseudo-random one-to-one circuit synthesis. United States Patent: 7,050,582, May 23, 2006.
  53. Medvedeva M.G., Aleshin S.V., Egorov E.E., Rodin S.B. Gradient method of mask edge correction. United States Patent: 7,039,896, May 2, 2006.
  54. Nikitin A.A., Andreev A.E. Decision function generator for a Viterbi decoder. United States Patent: 7,039,855, May 2, 2006.
  55. Andreev A.E., Nikitin A.A., Vikhliantsev I.A. Process and apparatus for placement of cells in an IC during floorplan creation. United States Patent: 7,036,102, April 25, 2006.
  56. Andreev A.E., Scepanovic R. FFS search and edit pipeline separation. United States Patent: 7,035,844, April 25, 2006.
  57. Medvedeva M.G., Kalinin J.V., Aleshin S.V., Strelkova N. Quality measurement of an aerial image. United States Patent: 7,035,446, April 25, 2006.
  58. Andreev A.E., Scepanovic R., Pavisic I., Vukovic V. RRAM backend flow. United States Patent: 7,028,274, April 11, 2006.
  59. Gasanov E.E., Podkolzin A.S., Galatenko A.V. Method and apparatus for finding optimal unification substitution for formulas in technology library. United States Patent: 7,003,739, February 21, 2006.
  60. Andreev A.E., Scepanovic R. Table module compiler equivalent to ROM. United States Patent: 7,003,510, February 21, 2006.
  61. Aleshin S.V., Medvedeva M.G., Rodin S.B., Egorov E.E. Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (OPC) purposes. United States Patent: 6,988,260, January 17, 2006.
  62. Andreev A.E., Scepanovic R. Universal gates for ICs and transformation of netlists for their implementation. United States Patent: 6,988,252, January 17, 2006.
  63. Andreev A.E., Vikhliantsev I.A., Pavisic I. Clock tree synthesis with skew for memory devices. United States Patent: 6,941,533, September 6, 2005.
  64. Andreev A.E., Vikhliantsev I.A., Ivanovic L.D. Built-in test for multiple memory circuits. United States Patent: 6,941,494, September 6, 2005.
  65. Andreev A.E., Scepanovic R. User selectable editing protocol for fast flexible search engine. United States Patent: 6,941,314, September 6, 2005.
  66. Gashkov S.B., Andreev A.E., Lu A. Optimization of adder based circuit architecture. United States Patent: 6,934,733, August 23, 2005.
  67. Aleshin S.V., Medvedeva M.G., Egorov E.E., Belokopytov G.V., Filseth P.G. Mask correction for photolithographic processes. United States Patent: 6,934,410, August 23, 2005.
  68. Aleshin S.V., Medvedeva M.G., Rodin S.B. Sidelobe correction for attenuated phase shift masks. United States Patent: 6,911,285, June 28, 2005.
  69. Nikitin A.A., Andreev A.E. Method for evaluating logic functions by logic circuits having optimized number of and/or switches. United States Patent: 6,901,573, May 31, 2005.
  70. Egorov E.E., Aleshin S.V., Scepanovic R. Method and system for constructing a hierarchy-driven chip covering for optical proximity correction. United States Patent: 6,898,780, May 24, 2005.
  71. Andreev E.A., Bolotov A.A., Scepanovic R., Andreev A.E. Memory that allows simultaneous read requests. United States Patent: 6,886,088, April 26, 2005.
  72. Gasanov E.E., Zolotykh A.A., Lu A. Method to find boolean function symmetries. United States Patent: 6,868,536, March 15, 2005.
  73. Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for optimizing the timing of integrated circuits. United States Patent: 6,868,535, March 15, 2005.
  74. Aleshin S.V., Medvedeva M.G., Kalinin J., Rodin S.B. First approximation for OPC significant speed-up. United States Patent: 6,854,104, February 8, 2005.
  75. Andreev A.E., Vikhliantsev; I.A. Netlist redundancy detection and global simplification. United States Patent: 6,848,094, January 25, 2005.
  76. Andreev A.E., Gasanov E.E., Scepanovic R. Multidirectional router. United States Patent: 6,845,495, January 18, 2005.
  77. Andreev A.E., Scepanovic R. Symbolic simulation driven netlist simplification. United States Patent: 6,842,750, January 11, 2005.
  78. Aleshin S.V., Egorov E.E., Medvedeva M.G. Optical proximity correction driven hierarchy. United States Patent: 6,813,758, November 2, 2004.
  79. Lu A., Pavisic I., Zolotykh A.A., Gasanov E.E. Process of restructuring logics in ICs for setup and hold time optimization. United States Patent: 6,810,515, October 26, 2004.
  80. Andreev A.E., Pavisic I., Scepanovic R. Process for layout of memory matrices in integrated circuits. United States Patent: 6,804,811, October 12, 2004.
  81. Andreev A.E., Scepanovic R. Method of decreasing instantaneous current without affecting timing. United States Patent: 6,795,954, September 21, 2004.
  82. Rodin S.B., Egorov E.E., Aleshin S.V. Automatic recognition of an optically periodic structure in an integrated circuit design. United States Patent: 6,785,871, August 31, 2004.
  83. Andreev A.E., Scepanovic R. Prefix comparator. United States Patent: 6,785,699, August 31, 2004.
  84. Andreev A.E., Pavisic I., Scepanovic R. Process layout of buffer modules in integrated circuits. United States Patent: 6,760,896, July 6, 2004.
  85. Andreev A.E., Ivanovic L., Pavisic I. Power routing with obstacles. United States Patent: 6,757,881, June 29, 2004.
  86. Andreev A.E., Scepanovic R. Editing protocol for flexible search engines. United States Patent: 6,735,600, May 11, 2004.
  87. Andreev A.E., Scepanovic R., Grinchuk M.I. Process for fast cell placement in integrated circuit design. United States Patent: 6,704,915, March 9, 2004.
  88. Nikitin A.A., Gasanov E.E., Zolotykh A.A. Overlap remover manager. United States Patent: 6,701,503, March 2, 2004.
  89. Gasanov E.E., Zolotykh A.A., Pavisic I., Lu A. Floor plan tester for integrated circuit design. United States Patent: 6,701,493, March 2, 2004.
  90. Gashkov S.B., Andreev A.E., Lu A. Optimization of comparator architecture. United States Patent: 6,691,283, February 10, 2004.
  91. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for dynamic buffer and inverter tree optimization. United States Patent: 6,681,373, January 20, 2004.
  92. Andreev A.E., Vukovic V. Spanning tree method for K-dimensional space. United States Patent: 6,665,850, December 16, 2003.
  93. Andreev A.E., Bolotov A.A., Scepanovic R. Fast free memory address controller. United States Patent: 6,662,287, December 9, 2003.
  94. Nikitin A.A., Zolotykh A.A., Radovanovic N. Direct transformation of engineering change orders to synthesized IC chip designs. United States Patent: 6,651,239, November 18, 2003.
  95. Gasanov E.E., Zolotykh A.A, Pavisic I., Lu A. Assignment of cell coordinates. United States Patent: 6,637,016, October 21, 2003.
  96. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for quick search for identities applicable to specified formula. United States Patent: 6,637,011, October 21, 2003.
  97. Gasanov E.E., Zolotykh A.A., Lu A., Pavisic I. Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells. United States Patent: 6,629,304, September 30, 2003.
  98. Gasanov E.E., Kudryavtsev V.B., Nikitin A.A. Blocked net buffer insertion. United States Patent: 6,615,401, September 2, 2003.
  99. Andreev A.E., Andreev E.A., Pavisic I. Optimal clock timing schedule for an integrated circuit. United States Patent: 6,615,397, September 2, 2003.
  100. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for formula area and delay minimization. United States Patent: 6,587,990, July 1, 2003.
  101. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for timing driven resynthesis. United States Patent: 6,564,361, May 13, 2003.
  102. Andreev A.E., Scepanovic R. Fast flexible search engine for longest prefix match. United States Patent: 6,564,211, May 13, 2003.
  103. Zolotykh A.A., Gasanov E.E., Pavisic I., Lu A. Timing recomputation. United States Patent: 6,553,551, April 22, 2003.
  104. Andreev A.E., Scepanovic R. Flexible search engine having sorted binary search tree for perfect match. United States Patent: 6,553,370, April 22, 2003.
  105. Lu A., Pavisic I., Zolotykh A.A., Gasanov E.E. Changing clock delays in an integrated circuit for skew optimization. United States Patent: 6,550,045, April 15, 2003.
  106. Pavisic I., Lu A., Zolotykh A.A., Gasanov E.E. Method in integrating clock tree synthesis and timing optimization for an integrated circuit design. United States Patent: 6,550,044, April 15, 2003.
  107. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for local resynthesis of logic trees with multiple cost functions. United States Patent: 6,543,032, April 1, 2003.
  108. Grinchuk M.I., Andreev A.E., Scepanovic R. Cell pin extensions for integrated circuits. United States Patent: 6,536,027, March 18, 2003.
  109. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for locating constants in combinational circuits. United States Patent: 6,536,016, March 18, 2003.
  110. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for optimal critical netlist area selection. United States Patent: 6,532,582, March 11, 2003.
  111. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for detecting equivalent and anti-equivalent pins. United States Patent: 6,530,063, March 4, 2003.
  112. Andreev A.E., Scepanovic R., Pavisic I. Chip core size estimation. United States Patent: 6,526,553, February 25, 2003.
  113. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for minimization of net delay by optimal buffer insertion. United States Patent: 6,519,746, February 11, 2003.
  114. Gasanov E.E., Zolotykh A.A., Postelga Yu.P. Density driven assignment of coordinates. United States Patent: 6,513,148, January 28, 2003.
  115. Andreev A.E., Bolotov A.A., Vikhliantsev I.A. Net delay optimization with ramptime violation removal. United States Patent: 6,507,939, January 14, 2003.
  116. Andreev A.E., Raspopovic P., Bolotov A.A. Channel router with buffer insertion. United States Patent: 6,505,336, January 7, 2003.
  117. Andreev A.E., Scepanovic R. Process, apparatus and program for transforming program language description of an IC to an RTL description. United States Patent: 6,487,698, November 26, 2002.
  118. Lu A., Pavisic I., Zolotykh A.A. Distribution dependent clustering in buffer insertion of high fanout nets. United States Patent: 6,487,697, November 26, 2002.
  119. Zolotykh A.A., Gasanov E.E., Pavisic I., Lu A. Parallelization of resynthesis. United States Patent: 6,470,487, October 22, 2002.
  120. Andreev A.E., Scepanovic R., Ivanovic L. epsilon-discrepant self-test technique. United States Patent: 6,467,067, October 15, 2002.
  121. Andreev A.E., Bolotov A.A., Raspopovic P. Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes. United States Patent: 6,453,453, September 17, 2002.
  122. Andreev A.E., Pavisic I., Raspopovic P. Wire routing optimization. United States Patent: 6,412,102, June 25, 2002.
  123. Rostoker M.D., Koford J.S., Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal architecture. United States Patent: 6,407,434, June 18, 2002.
  124. Andreev A.E., Gasanov E.E., Scepanovic R., Raspopovic P. Method and apparatus for parallel simultaneous global and detail routing. United States Patent: 6,324,674, November 27, 2001.
  125. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Programmable triangular shaped device having variable gain. United States Patent: 6,312,980, November 6, 2001.
  126. Scepanovic R., Pavisic I., Koford J.S., Andreev A.E., Jones E. Advanced modular cell placement system. United States Patent: 6,292,929, September 18, 2001.
  127. Pavisic I., Bolotov A.A., Andreev A.E., Scepanovic R. Modifying timing graph to avoid given set of paths. United States Patent: 6,292,924, September 18, 2001.
  128. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for local optimization of the global routing. United States Patent: 6,289,495, September 11, 2001.
  129. Aleshin S.V., Egorov E., Belokopitov G.V., Petranovic D. Geometric aerial image simulation. United States Patent: 6,263,299, July 17, 2001.
  130. Raspopovic; P., Scepanovic R., Andreev A.E. Method and apparatus for coarse global routing. United States Patent: 6,260,183, July 10, 2001.
  131. Gasanov E.E., Scepanovic R., Raspopovic P., Andreev A.E. Net routing using basis element decomposition. United States Patent: 6,253,363, June 26, 2001.
  132. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for parallel Steiner tree routing. United States Patent: 6,247,167, June 12, 2001.
  133. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for minimization of process defects while routing. United States Patent: 6,230,306, May 8, 2001.
  134. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with overlap remover with minimal noise. United States Patent: 6,223,332, April 24, 2001.
  135. Aleshin S.V., Belokopitov G.V., Scepanovic R. Mask having an arbitrary complex transmission function. United States Patent: 6,197,456, March 6, 2001.
  136. Andreev A.E., Pavisic I., Scepanovic R. Method and apparatus for determining wire routing. United States Patent: 6,186,676, February 13, 2001.
  137. Andreev A.E., Pavisic I., Raspopovic P. Metal layer assignment. United States Patent: 6,182,272, January 30, 2001.
  138. Scepanovic R., Andreev A.E., Gasanov E.E., Raspopovic P. Method and apparatus for hierarchical global routing descend. United States Patent: 6,175,950, January 16, 2001.
  139. Scepanovic R., Andreev A.E., Raspopovic P. Memory-saving method and apparatus for partitioning high fanout nets. United States Patent: 6,154,874, November 28, 2000.
  140. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. United States Patent: 6,134,702, October 17, 2000.
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