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 Publications Publications of electronic articles in English
 Patents Patents of the MaTIS chair scientists
 Research Main directions of scientific research
 Conference International Conference "Intelligent Systems and Computer Sciences"

Patents of the MaTIS chair scientists

 

US Patents

  1. Andreev A.E., Vikhliantsev I.A., Pavisic I. Clock tree synthesis with skew for memory devices. United States Patent: 6,941,533, September 6, 2005.
  2. Andreev A.E., Vikhliantsev I.A., Ivanovic L.D. Built-in test for multiple memory circuits. United States Patent: 6,941,494, September 6, 2005.
  3. Andreev A.E., Scepanovic R. User selectable editing protocol for fast flexible search engine. United States Patent: 6,941,314, September 6, 2005.
  4. Gashkov S.B., Andreev A.E., Lu A. Optimization of adder based circuit architecture. United States Patent: 6,934,733, August 23, 2005.
  5. Aleshin S.V., Medvedeva M.G., Egorov E.E., Belokopytov G.V., Filseth P.G. Mask correction for photolithographic processes. United States Patent: 6,934,410, August 23, 2005.
  6. Aleshin S.V., Medvedeva M.G., Rodin S.B. Sidelobe correction for attenuated phase shift masks. United States Patent: 6,911,285, June 28, 2005.
  7. Nikitin A.A., Andreev A.E. Method for evaluating logic functions by logic circuits having optimized number of and/or switches. United States Patent: 6,901,573, May 31, 2005.
  8. Egorov E.E., Aleshin S.V., Scepanovic R. Method and system for constructing a hierarchy-driven chip covering for optical proximity correction. United States Patent: 6,898,780, May 24, 2005.
  9. Andreev E.A., Bolotov A.A., Scepanovic R., Andreev A.E. Memory that allows simultaneous read requests. United States Patent: 6,886,088, April 26, 2005.
  10. Gasanov E.E., Zolotykh A.A., Lu A. Method to find boolean function symmetries. United States Patent: 6,868,536, March 15, 2005.
  11. Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for optimizing the timing of integrated circuits. United States Patent: 6,868,535, March 15, 2005.
  12. Aleshin S.V., Medvedeva M.G., Kalinin J., Rodin S.B. First approximation for OPC significant speed-up. United States Patent: 6,854,104, February 8, 2005.
  13. Andreev A.E., Vikhliantsev; I.A. Netlist redundancy detection and global simplification. United States Patent: 6,848,094, January 25, 2005.
  14. Andreev A.E., Gasanov E.E., Scepanovic R. Multidirectional router. United States Patent: 6,845,495, January 18, 2005.
  15. Andreev A.E., Scepanovic R. Symbolic simulation driven netlist simplification. United States Patent: 6,842,750, January 11, 2005.
  16. Aleshin S.V., Egorov E.E., Medvedeva M.G. Optical proximity correction driven hierarchy. United States Patent: 6,813,758, November 2, 2004.
  17. Lu A., Pavisic I., Zolotykh A.A., Gasanov E.E. Process of restructuring logics in ICs for setup and hold time optimization. United States Patent: 6,810,515, October 26, 2004.

  18. Andreev A.E., Pavisic I., Scepanovic R. Process for layout of memory matrices in integrated circuits. United States Patent: 6,804,811, October 12, 2004.

  19. Andreev A.E., Scepanovic R. Method of decreasing instantaneous current without affecting timing. United States Patent: 6,795,954, September 21, 2004.

  20. Rodin S.B., Egorov E.E., Aleshin S.V. Automatic recognition of an optically periodic structure in an integrated circuit design. United States Patent: 6,785,871, August 31, 2004.
  21. Andreev A.E., Scepanovic R. Prefix comparator. United States Patent: 6,785,699, August 31, 2004.

  22. Andreev A.E., Pavisic I., Scepanovic R. Process layout of buffer modules in integrated circuits. United States Patent: 6,760,896, July 6, 2004.

  23. Andreev A.E., Ivanovic L., Pavisic I. Power routing with obstacles. United States Patent: 6,757,881, June 29, 2004.

  24. Andreev A.E., Scepanovic R. Editing protocol for flexible search engines. United States Patent: 6,735,600, May 11, 2004.

  25. Andreev A.E., Scepanovic R., Grinchuk M.I. Process for fast cell placement in integrated circuit design. United States Patent: 6,704,915, March 9, 2004.

  26. Nikitin A.A., Gasanov E.E., Zolotykh A.A. Overlap remover manager. United States Patent: 6,701,503, March 2, 2004.

  27. Gasanov E.E., Zolotykh A.A., Pavisic I., Lu A. Floor plan tester for integrated circuit design. United States Patent: 6,701,493, March 2, 2004.

  28. Gashkov S.B., Andreev A.E., Lu A. Optimization of comparator architecture. United States Patent: 6,691,283, February 10, 2004.

  29. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for dynamic buffer and inverter tree optimization. United States Patent: 6,681,373, January 20, 2004.

  30. Andreev A.E., Vukovic V. Spanning tree method for K-dimensional space. United States Patent: 6,665,850, December 16, 2003.

  31. Andreev A.E., Bolotov A.A., Scepanovic R. Fast free memory address controller. United States Patent: 6,662,287, December 9, 2003.

  32. Nikitin A.A., Zolotykh A.A., Radovanovic N. Direct transformation of engineering change orders to synthesized IC chip designs. United States Patent: 6,651,239, November 18, 2003.

  33. Gasanov E.E., Zolotykh A.A, Pavisic I., Lu A. Assignment of cell coordinates. United States Patent: 6,637,016, October 21, 2003.

  34. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for quick search for identities applicable to specified formula. United States Patent: 6,637,011, October 21, 2003.

  35. Gasanov E.E., Zolotykh A.A., Lu A., Pavisic I. Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells. United States Patent: 6,629,304, September 30, 2003.

  36. Gasanov E.E., Kudryavtsev V.B., Nikitin A.A. Blocked net buffer insertion. United States Patent: 6,615,401, September 2, 2003.

  37. Andreev A.E., Andreev E.A., Pavisic I. Optimal clock timing schedule for an integrated circuit. United States Patent: 6,615,397, September 2, 2003.

  38. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for formula area and delay minimization. United States Patent: 6,587,990, July 1, 2003.

  39. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for timing driven resynthesis. United States Patent: 6,564,361, May 13, 2003.

  40. Andreev A.E., Scepanovic R. Fast flexible search engine for longest prefix match. United States Patent: 6,564,211, May 13, 2003.

  41. Zolotykh A.A., Gasanov E.E., Pavisic I., Lu A. Timing recomputation. United States Patent: 6,553,551, April 22, 2003.

  42. Andreev A.E., Scepanovic R. Flexible search engine having sorted binary search tree for perfect match. United States Patent: 6,553,370, April 22, 2003.

  43. Lu A., Pavisic I., Zolotykh A.A., Gasanov E.E. Changing clock delays in an integrated circuit for skew optimization. United States Patent: 6,550,045, April 15, 2003.

  44. Pavisic I., Lu A., Zolotykh A.A., Gasanov E.E. Method in integrating clock tree synthesis and timing optimization for an integrated circuit design. United States Patent: 6,550,044, April 15, 2003.

  45. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for local resynthesis of logic trees with multiple cost functions. United States Patent: 6,543,032, April 1, 2003.

  46. Grinchuk M.I., Andreev A.E., Scepanovic R. Cell pin extensions for integrated circuits. United States Patent: 6,536,027, March 18, 2003.

  47. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for locating constants in combinational circuits. United States Patent: 6,536,016, March 18, 2003.

  48. Zolotykh A.A., Gasanov E.E., Podkolzin A.S., Kudryavtsev V.B. Method and apparatus for optimal critical netlist area selection. United States Patent: 6,532,582, March 11, 2003.

  49. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for detecting equivalent and anti-equivalent pins. United States Patent: 6,530,063, March 4, 2003.

  50. Andreev A.E., Scepanovic R., Pavisic I. Chip core size estimation. United States Patent: 6,526,553, February 25, 2003.

  51. Andreev A.E., Scepanovic R., Bolotov A.A. Method and apparatus for minimization of net delay by optimal buffer insertion. United States Patent: 6,519,746, February 11, 2003.

  52. Gasanov E.E., Zolotykh A.A., Postelga Yu.P. Density driven assignment of coordinates. United States Patent: 6,513,148, January 28, 2003.

  53. Andreev A.E., Bolotov A.A., Vikhliantsev I.A. Net delay optimization with ramptime violation removal. United States Patent: 6,507,939, January 14, 2003.

  54. Andreev A.E., Raspopovic P., Bolotov A.A. Channel router with buffer insertion. United States Patent: 6,505,336, January 7, 2003.

  55. Andreev A.E., Scepanovic R. Process, apparatus and program for transforming program language description of an IC to an RTL description. United States Patent: 6,487,698, November 26, 2002.

  56. Lu A., Pavisic I., Zolotykh A.A. Distribution dependent clustering in buffer insertion of high fanout nets. United States Patent: 6,487,697, November 26, 2002.

  57. Zolotykh A.A., Gasanov E.E., Pavisic I., Lu A. Parallelization of resynthesis. United States Patent: 6,470,487, October 22, 2002.

  58. Andreev A.E., Scepanovic R., Ivanovic L. epsilon-discrepant self-test technique. United States Patent: 6,467,067, October 15, 2002.

  59. Andreev A.E., Bolotov A.A., Raspopovic P. Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes. United States Patent: 6,453,453, September 17, 2002.

  60. Andreev A.E., Pavisic I., Raspopovic P. Wire routing optimization. United States Patent: 6,412,102, June 25, 2002.

  61. Rostoker M.D., Koford J.S., Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal architecture. United States Patent: 6,407,434, June 18, 2002.

  62. Andreev A.E., Gasanov E.E., Scepanovic R., Raspopovic P. Method and apparatus for parallel simultaneous global and detail routing. United States Patent: 6,324,674, November 27, 2001.

  63. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Programmable triangular shaped device having variable gain. United States Patent: 6,312,980, November 6, 2001.

  64. Scepanovic R., Pavisic I., Koford J.S., Andreev A.E., Jones E. Advanced modular cell placement system. United States Patent: 6,292,929, September 18, 2001.

  65. Pavisic I., Bolotov A.A., Andreev A.E., Scepanovic R. Modifying timing graph to avoid given set of paths. United States Patent: 6,292,924, September 18, 2001.

  66. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for local optimization of the global routing. United States Patent: 6,289,495, September 11, 2001.

  67. Aleshin S.V., Egorov E., Belokopitov G.V., Petranovic D. Geometric aerial image simulation. United States Patent: 6,263,299, July 17, 2001.

  68. Raspopovic; P., Scepanovic R., Andreev A.E. Method and apparatus for coarse global routing. United States Patent: 6,260,183, July 10, 2001.

  69. Gasanov E.E., Scepanovic R., Raspopovic P., Andreev A.E. Net routing using basis element decomposition. United States Patent: 6,253,363, June 26, 2001.

  70. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for parallel Steiner tree routing. United States Patent: 6,247,167, June 12, 2001.

  71. Raspopovic P., Scepanovic R., Andreev A.E. Method and apparatus for minimization of process defects while routing. United States Patent: 6,230,306, May 8, 2001.

  72. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with overlap remover with minimal noise. United States Patent: 6,223,332, April 24, 2001.

  73. Aleshin S.V., Belokopitov G.V., Scepanovic R. Mask having an arbitrary complex transmission function. United States Patent: 6,197,456, March 6, 2001.

  74. Andreev A.E., Pavisic I., Scepanovic R. Method and apparatus for determining wire routing. United States Patent: 6,186,676, February 13, 2001.

  75. Andreev A.E., Pavisic I., Raspopovic P. Metal layer assignment. United States Patent: 6,182,272, January 30, 2001.

  76. Scepanovic R., Andreev A.E., Gasanov E.E., Raspopovic P. Method and apparatus for hierarchical global routing descend. United States Patent: 6,175,950, January 16, 2001.

  77. Scepanovic R., Andreev A.E., Raspopovic P. Memory-saving method and apparatus for partitioning high fanout nets. United States Patent: 6,154,874, November 28, 2000.

  78. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. United States Patent: 6,134,702, October 17, 2000.

  79. Pavisic I., Scepanovic R., Andreev A.E. Method and apparatus for horizontal congestion removal. United States Patent: 6,123,736, September 26, 2000.

  80. Petranovic D., Scepanovic R., Aleshin S.V., Grinchuk M.I., Gashkov S.B. Resynthesis method for significant delay reduction. United States Patent: 6,109,201, August 29, 2000.

  81. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Triangular semiconductor or gate. United States Patent: 6,097,073, August 1, 2000.

  82. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with sinusoidal optimization. United States Patent: 6,085,032, July 4, 2000.

  83. Pavisic I., Scepanovic R., Andreev A.E. Method and apparatus for continuous column density optimization. United States Patent: 6,075,933, June 13, 2000.

  84. Andreev A.E., Pavisic I., Scepanovic R. Method and apparatus for congestion driven placement. United States Patent: 6,070,108, May 30, 2000.

  85. Scepanovic R., Pavisic I., Koford J.S., Andreev A.E., Jones E. Advanced modular cell placement system. United States Patent: 6,067,409, May 23, 2000.

  86. Scepanovic R., Andreev A.E., Pavisic I. Method and apparatus for vertical congestion removal. United States Patent: 6,058,254, May 2, 2000.

  87. Scepanovic R., Koford J,S., Andreev A.E., Pavisic I. Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization. United States Patent: 6,038,385, March 14, 2000.

  88. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with median control and increase in resolution. United States Patent: 6,030,110, February 29, 2000.

  89. Scepanovic R., Andreev A.E., Pavisic I. Parallel processing of Integrated circuit pin arrival times. United States Patent: 6,000,038, December 7, 1999.

  90. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Architecture having diamond shaped or parallelogram shaped cells. United States Patent: 5,973,376, October 26, 1999.

  91. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with optimization of cell neighborhood system. United States Patent: 5,971,588, October 26, 1999.

  92. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with functional sieve optimization technique. United States Patent: 5,963,455, October 5, 1999.

  93. Scepanovic R., Jones E., Andreev A.E.. Parallel processor implementation of net routing. United States Patent: 5,930,500, July 27, 1999.

  94. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with coarse overflow remover. United States Patent: 5,914,888, June 22, 1999.

  95. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S., Roseboom E.M. Physical design automation system and process for designing integrated circuit chips using highly parallel sieve optimization with multiple "jiggles". United States Patent: 5,909,376, June 1, 1999.

  96. Scepanovic R., Andreev A.E., Pavisic I. Integrated circuit floor plan optimization system. United States Patent: 5,898,597, April 27, 1999.

  97. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with iterative one dimensional preplacement optimization. United States Patent: 5,892,688, April 6, 1999.

  98. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Tri-directional interconnect architecture for SRAM. United States Patent: 5,889,329, March 30, 1999.

  99. Scepanovic R., Andreev A.E., Pavisic I. Integrated circuit cell placement parallelization with minimal number of conflicts. United States Patent: 5,875,118, February 23, 1999.

  100. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system. United States Patent: 5,872,718, February 16, 1999.

  101. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal sense cell architecture. United States Patent: 5,872,380, February 16, 1999.

  102. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with dispersion-driven levelizing system. United States Patent: 5,870,312, February 9, 1999.

  103. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with fast procedure for finding a levelizing cut point. United States Patent: 5,870,311, February 9, 1999.

  104. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with density driven capacity penalty system. United States Patent: 5,867,398, February 2, 1999.

  105. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Triangular semiconductor NAND gate. United States Patent: 5,864,165, January 26, 1999.

  106. Scepanovic R., Andreev A.E., Pavisic I. Efficient multiprocessing for cell placement of integrated circuits. United States Patent: 5,859,782, January 12, 1999.

  107. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with universal affinity driven discrete placement optimization. United States Patent: 5,844,811, December 1, 1998.

  108. Scepanovic R., Koford J.S., Kudryavtsev V.B., Aleshin S.V., Andreev A.E., Podkolzin A.S. Physical design automation system and method using monotonically improving linear clusterization. United States Patent: 5,838,585, November 17, 1998.

  109. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with minimizing maximal cut driven affinity system. United States Patent: 5,835,381, November 10, 1998.

  110. Scepanovic R., Koford J.S., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S., Boyle D.B. Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip. United States Patent: 5,835,378, November 10, 1998.

  111. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Triangular semiconductor "AND" gate device. United States Patent: 5,834,821, November 10, 1998.

  112. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with wire length driven affinity system. United States Patent: 5,831,863, November 3, 1998.

  113. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. CAD for hexagonal architecture. United States Patent: 5,822,214, October 13, 1998.

  114. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with neighborhood system driven optimization. United States Patent: 5,812,740, September 22, 1998.

  115. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Transistors having dynamically adjustable characteristics. United States Patent: 5,811,863, September 22, 1998.

  116. Scepanovic R., Koford J.S., Andreev A.E. Advanced modular cell placement system with cell placement crystallization. United States Patent: 5,808,899, September 15, 1998.

  117. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Polydirectional non-orthoginal three layer interconnect architecture. United States Patent: 5,808,330, September 15, 1998.

  118. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal SRAM architecture. United States Patent: 5,801,422, September 1, 1998.

  119. Scepanovic R., Koford J.S., Andreev A.E., Pavisic I. Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization. United States Patent: 5,796,625, August 18, 1998.

  120. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal architecture with triangular shaped cells. United States Patent: 5,789,770, August 4, 1998.

  121. Scepanovic R., Koford J.S., Jones E.R., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using generalized assignment. United States Patent: 5,784,287, July 21, 1998.

  122. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal field programmable gate array architecture. United States Patent: 5,777,360, July 7, 1998.

  123. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Hexagonal DRAM array. United States Patent: 5,742,086, April 21, 1998.

  124. Scepanovic R., Koford J.S., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S., Roseboom E.M. Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization. United States Patent: 5,712,793, January 27, 1998.

  125. Scepanovic R., Koford J.S., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints. United States Patent: 5,699,265, December 16, 1997.

  126. Scepanovic R., Koford J.S., Kudryvavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters. United States Patent: 5,661,663, August 26, 1997.

  127. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Microelectronic integrated circuit including triangular semiconductor "or" g. United States Patent: 5,654,563, August 5, 1997.

  128. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Microelectronic integrated circuit including triangular CMOS "nand" gate device. United States Patent: 5,650,653, July 22, 1997.

  129. Rostoker M.D., Koford J.S.,Scepanovic R., Jones E.R., Padmanahben G.R., Kapoor A.K., Kudryavtsev V.B., Andreev A.E., Aleshin S.V., Podkolzin A.S. Microelectronic integrated circuit including triangular semiconductor "and" gate device. United States Patent 5,631,581, May 20, 1997.

 

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